The field of invention relates to semiconductor memory technology generally; and more specifically, to an apparatus and method for a memory storage cell leakage cancellation scheme.
FIG. 1 shows a prior art Random Access Memory (RAM) cell 100. The prior art RAM cell 100 of FIG. 1 includes a plurality of xe2x80x9cNxe2x80x9d storage cells S1 through SN (each of which may correspond to static RAM (SRAM) cells). Each of the storage cells S1 through SN stores a bit of data. Data is read from a particular storage cell by activating its corresponding word line (WL) (e.g., WL1 for storage cell S1, WL2 for S2, etc.). During a typical storage cell read operation, the bit lines 101, 102 are pre-charged to a xe2x80x9chighxe2x80x9d voltage.
The word line of the storage cell to be read (e.g., word line WL1 for storage cell S1) is activated (e.g., with a xe2x80x9chighxe2x80x9d voltage) while the word lines for the remaining xe2x80x9cun readxe2x80x9d storage cells (e.g., word lines WL2 through WLN for storage cells S2 through SN, respectively) are deactivated (e.g., with a xe2x80x9clowxe2x80x9d voltage). Upon the activation of the word line for the storage cell to be read (e.g., word line WL1 for storage cell S1), the storage cell to be read drives one of the bit lines to a xe2x80x9clowxe2x80x9d voltage.
For example, if the data stored in storage cell S1 corresponds to a xe2x80x9c1xe2x80x9d, storage cell S1 drives bit line 102 to a xe2x80x9clowxe2x80x9d voltage while bit line 101 remains at the pre-charged xe2x80x9chighxe2x80x9d voltage. By contrast, if the data stored in storage cell S1 corresponds to a xe2x80x9c0xe2x80x9d, storage cell S1 drives bit line 101 to a xe2x80x9clowxe2x80x9d voltage while bit line 102 remains at the pre-charged xe2x80x9chighxe2x80x9d voltage. FIG. 1 shows an example of the later case (i.e., storage cell S1 has a xe2x80x9c0xe2x80x9d stored) because drive current Isc is observed being driven from bit line 101 by storage cell S1.
Because the voltages on the bit lines 101, 102 during a storage cell read are different (i.e., one voltage being high, the other voltage being low), a differential signal may be said to exist on the bit lines 101, 102. The differential signal provided on the bit lines 101, 102 may be expressed as:
Signal=V1-V2xe2x80x83xe2x80x83Eqn.1 
where V1 is the voltage on bit line 101 and V2 is the voltage on bit line 102. Note that the actual high and low voltages on the bit lines may vary from embodiment to embodiment. Furthermore, note that the greater the difference between V1 and V2, the greater the differential signal observed on the bit lines 101, 102.
Storage cell leakage may cause an increase in the amount of time it takes the differential voltage to develop on the bit lines 101, 102 during a bit cell read. As such, the speed of operation of the RAM cell 100 may be adversely affected by the storage cell leakage. The rate at which the differential voltage is created during the course of a storage cell read, without storage cell leakage, may be expressed as:
Dv/Dt=Isc/(Cb+2Cc)xe2x80x83xe2x80x83Eqn. 2
where: 1) Cb is the capacitance of the bit line being pulled down; 2) Cc is the capacitance between the bit lines 101, 102; and 3) Isc is the amount of drive current pulled by a storage cell being read from.
From Equation 2, it is apparent that the rate at which the differential voltage is created increases as Isc increases. Storage cell leakage has the effect of the reducing the Isc term in Equation 2 and, as such, reduces the rate at which the differential voltage is created. Storage cell leakage is the tendency of a storage cell, that is not being read from, to pull current from a bit line. As the number of xe2x80x9cun-readxe2x80x9d cells that pull leakage current from the xe2x80x9chighxe2x80x9d bit line increases, the impact on the rate at which the differential voltage worsens.
A worse case condition is exemplified in FIG. 1. Specifically, during a read of storage cell S1 which pulls current Isc from the low bit line 101, each of the remaining Nxe2x88x921 storage cells (i.e., storage cells S2 through SN) pull leakage current IL from the high bit line 102. Each leakage current IL from the high bit line 102 will cause a drop in the high bit line 102 voltage. As such, Nxe2x88x921 leakage currents IL from the high bit line 102 (as seen in FIG. 1) corresponds to a worst case voltage drop on the high bit line 102.
From the perspective of the differential voltage being established between the pair of bit lines 101 and 102, as the high bit line 102 voltage drops from the Nxe2x88x921 leakage currents IL, the effect of dropping the low bit line 101 voltage with the drive current Isc is reduced. This corresponds to a decrease in the differential signal voltage which corresponds to a decrease in the rate at which the differential signal voltage is developed.
That is, for the worst case condition shown in FIG. 1, the rate at which the differential voltage is created during the course of a storage cell read, with storage cell leakage, may be expressed as:
Dv/Dt=(Iscxe2x88x92(Nxe2x88x921)IL)/(Cb+2Cc)xe2x80x83xe2x80x83Eqn. 3
where: 1) Cb is the capacitance of the bit line being pulled down; 2) Cc is the capacitance between the bit lines 101, 102; 3) Isc is the amount of drive current pulled by a storage cell being read from; and 4) (Nxe2x88x921)IL is the total amount of leakage current being pulled from the high bit line 102. As seen in Equation 3, the leakage current term (Nxe2x88x921)IL subtracts from the drive current term Isc. This corresponds to a drop in the rate at which the differential voltage is developed. As discussed, this corresponds to a drop in the speed of the RAM cell 100.